1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an SOI (Silicon On Insulator) structure.
2. Description of the Background Art
In recent years, a device having a plurality of semiconductor integrated circuits (for example, memories and system LSIs) formed on a semiconductor substrate has been fabricated. In some of such devices, a plurality of semiconductor integrated circuits formed on a semiconductor substrate share a small number of power supply potential pins/ground potential pins.
However, it is expected that, due to potential reduction in power supply potential/ground potential within a device, the device is prone to adverse effects caused by power supply potential noise and ground potential noise, leading to deteriorated electrical characteristics of the semiconductor device as a whole. Since a signal line which connects devices (for example, data bus) occupies a large interconnection area, it is difficult to increase the cross-sectional areas of a power supply potential interconnection and a ground potential interconnection to reduce interconnection resistance. In addition, in a device having a large stepped portion such as a DRAM (Dynamic Random Access Memory) cell, there is a limit to providing multiple layers of metal interconnections over a transistor.